A
STUDY ON THE PERFORMANCE OF A THREE-STAGE LOAD-BALANCING SWITCH
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ABSTRACT:
There has been a great
deal of interest recently in load-balancing switches due to their simple
architecture and high forwarding bandwidth. Nevertheless, the mis-sequencing problem
of the original load-balancing switch hinders the performance of underlying TCP
applications. Several load-balancing switch designs have been proposed to
address this mis-sequencing issue. They solve this mis-sequencing problem at
the cost of either algorithmic complexity or special hardware requirements. In this
paper, we address the mis-sequencing problem by introducing a three-stage
load-balancing switch architecture enhanced with an output load-balancing
mechanism. This three-stage load-balancing switch achieves a high forwarding
capacity while preserving the order of packets without the need of costly
online scheduling algorithms. Theoretical analyses and simulation results show
that this three-stage load-balancing switch provides a transmission delay that
is upper-bounded by that of an output-queued switch plus a constant that
depends only on the number of input/output ports, indicating the same
forwarding capacity as an output-queued switch.
EXISTING SYSTEM:
There has been a great
deal of interest recently in load balancing switches due to their simple
architecture and high forwarding capacity. A typical load-balancing switch
consists of a two-stage switching fabric and a one-stage buffer sandwiched between
the two switch fabrics where each fabric executes a periodic connection pattern.
The idea behind this kind of design is that the input traffic with an arbitrary
distribution becomes uniformly distributed through the first-stage switch
fabric and then is fully forwarded by the second-stage switch fabric. Thus,
high throughput is achieved while the architecture remains scalable. However, such
a load-balancing switch suffers amis-sequencing problem; that is, the order of packets may not be preserved during the
transmission process. Mis-sequencing is undesirable because it hinders the
efficiency of TCP connections.
DISADVANTAGES OF
EXISTING SYSTEM:
· It
has mis-sequencing problem.
·
It is more costly.
·
It is not scalable.
PROPOSED SYSTEM:
In this paper, we introduce a new load-balancing
switch, called the three-stage load-balancing (3SLB) switch, which effectively
solves the mis-sequencing problem without the need of costly online scheduling
algorithms or hardware speedup. The switch architecture studied in this paper
was originally proposed by Wang. The work presented in this paper significantly
extends these initial efforts, providing a thorough theoretical analysis and
evaluating its performance through extensive simulations. The most significant
difference between the 3SLB switch and prior load-balancing switches is the
third stage of the 3SLB switch in which packets are buffered in an output
load-balancing fashion and forwarded in order of ascending arrival time. With the
third stage, the order of packets is preserved without using any complex real-time
scheduling algorithm; the overall online scheduling complexity of the 3SLB
switch. Thus, the 3SLB switch retains the scalability of prior load-balancing switches.
ADVANTAGES OF PROPOSED
SYSTEM:
·
The complexity of the online scheduling
algorithm inside a 3LSB switch is , and no hardware speedup is required.
·
Low average delay: By simulation, we
show that the 3SLB switch has a much lower average delay than existing IQ switches
under heavy inputs as well as bursty inputs.
SYSTEM ARCHITECTURE:
SYSTEM CONFIGURATION:-
HARDWARE REQUIREMENTS:-
ü Processor - Pentium –IV
ü Speed - 1.1 Ghz
ü RAM - 512 MB(min)
ü Hard
Disk - 40 GB
ü Key
Board - Standard Windows Keyboard
ü Mouse - Two or Three Button Mouse
ü Monitor - LCD/LED
SOFTWARE
REQUIREMENTS:
•
Operating system : Windows XP
•
Coding Language : Java
•
Data Base : MySQL
•
Tool : Net Beans IDE
REFERENCE:
Yan Cai, Xiaolin Wang, Weibo Gong, and
Don Towsley, “A Study on the Performance of a
Three-Stage Load-Balancing Switch” IEEE/ACM TRANSACTIONS
ON NETWORKING, VOL. 22, NO. 1, FEBRUARY 2014.
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